The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, the properties and behaviors of semiconductor structures and materials.
For some time now, the phenomenon of electrostatic discharge (ESD) has created a number of problems for manufacturers and end-users of semiconductor technology. ESD may be defined as the transfer of charge between bodies at different electrical potentials. The magnitude of such differing potentials is expressed as a voltage. ESD voltages can vary across a wide range of extreme voltages (e.g., ˜100 V-30000 V), depending upon a number of variables.
Occurrences of ESD—sometimes referred to as “ESD events”—can be caused by any number of routine procedures or happenings, commonly requiring only contact and separation of two materials. ESD events include electrostatic discharges to and from a device, as well as field induction discharges. Given their relatively large magnitude, and the relative ease with which they occur, efforts to minimize ESD events have been made for some time now.
Even so, as semiconductor device structures and geometries are reduced, their sensitivity and susceptibility to ESD events increases. ESD events can drastically alter or damage the electrical characteristics of a semiconductor device—degrading or destroying it. Damage caused by ESD can be catastrophic (and immediate) or latent in nature. Latent defects can result in a number of reliability and repair problems in end equipment use. Whether ESD-induced damage is immediate or latent in nature, a damaged device is usually scrapped or replaced. Thus, even where ESD events occur only infrequently, losses can—over time—be substantial.
In addition to efforts made to reduce the occurrence of ESD events, efforts have also been made to mitigate the physical damage caused by ESD. Among semiconductor manufacturers, such efforts have included the utilization of circuitry components that are inherently capable of withstanding or dissipating ESD discharges without being damaged. One such structure that is frequently utilized is the silicon-controlled rectifier (SCR).
SCRs may be implemented in a number of ways. In a CMOS-based technology, for example, an SCR structure may comprise a P-N-P-N junction. The performance characteristics of most SCRs, however, are generally similar—especially with regards to ESD protection. Most SCRs are designed such that they are capable of dissipating a high level of voltage at relatively low current. Once the voltage (and current) discharged reaches a certain level (i.e., a voltage threshold), the SCR transitions into a low voltage hold state. This hold state is at a voltage level lower than the device's normal operating voltage. As the ESD event occurs, the SCR structure remains in the hold state until the ESD discharge dissipates. Most ESD events are temporally short, and usually occur—in a semiconductor manufacturing environment—when the device itself is powered off.
Unfortunately, however, many conventional SCR structures can experience latch-up problems during normal operation of the device in which the SCR is implemented. In a number of integrated circuits (ICs), the operational voltage range of a device is well below the hold-state voltage threshold of the SCR structure. Even where operational anomalies—such as electrical signal noise or stresses—are present, operational voltages do not exceed the hold-state voltage threshold. In a growing number of applications (e.g., power ICs, etc.), however, device operational voltages are significant, and well within a nominal range of the hold-state voltage threshold. Thus, minor signal noise or electrical stress can push the device past the threshold and into a hold-state latch-up. This can cause the device to latch up, negatively impacting device and system performance.
As a result, there is a need for a versatile system that readily provides SCR-based ESD protection, while obviating operational latch-up problems, for IC designs in an easy, efficient and cost-effective manner.